MLCC Dielectric Layer Thickness Test & Optimization

Technical Background of MLCC Dielectric Layer

Multi-Layer Ceramic Capacitor (MLCC) is one of the core passive components in electronic circuits. Its core structure is formed by alternating lamination and high-temperature sintering of multiple ceramic dielectric layers and internal electrodes. As the core carrier for charge storage, the thickness of the dielectric layer directly determines the capacitance density, voltage withstand performance and reliability of MLCC. Driven by the demand for miniaturization and high integration of electronic equipment, reducing the thickness of dielectric layer has become the key technical direction to improve the capacitance per unit volume of MLCC. This test focuses on the impact of dielectric layers with different thicknesses on the core performance of MLCC. All data are derived from standardized laboratory tests, with samples covering brand-free universal MLCC of different thickness specifications. The test environment is 25℃ and 50%RH, and the test equipment is high-precision LCR tester and Scanning Electron Microscope (SEM).

Measuring Method of Dielectric Layer Thickness

A cross-section observation method was adopted for accurate measurement of MLCC dielectric layer thickness in this test: first, the tested MLCC samples were cut without damage by a diamond cutter to expose the internal laminated structure, then the cutting surface was ground and polished to remove burrs and damaged layers caused by cutting; SEM was then used to image the polished cross-section with a magnification of 5000 times, and the central area of the sample was selected as the observation surface, the edge area is susceptible to process deviation and is not included in valid data; image analysis software was finally used to measure the dielectric layers in SEM images layer by layer. For each thickness specification, 20 independent MLCC samples were selected, and 100 dielectric layer measuring points were selected for each sample. The arithmetic mean value was calculated after removing the maximum and minimum values, and the actual thickness value of dielectric layers of each specification was obtained with a measurement accuracy of up to 0.01μm. During the test, to avoid human error, all operations were independently completed by 3 testers, and the data deviation was controlled within ±0.05μm.

In addition to the basic thickness measurement, auxiliary tests on the density and uniformity of the dielectric layer were carried out synchronously: the density was measured by the Archimedes drainage method, and the uniformity was characterized by calculating the thickness standard deviation of 100 measuring points in the same sample, with a standard deviation ≤ 0.08μm judged as qualified uniformity. Three core thickness specifications were selected in this test: 1μm, 2μm and 3μm, all of which are the mainstream R&D and commercial dielectric layer thickness ranges in the current industry.

Performance Data of Dielectric Layers with Different Thicknesses

1. Capacitance density: Capacitance density refers to the capacitance per unit volume of MLCC, which is the core index to measure the optimization effect of dielectric layer thickness. The test data show that the capacitance density of MLCC with 3μm dielectric layer is 2.5μF/mm³, that of 2μm dielectric layer increases to 4.8μF/mm³, and that of 1μm dielectric layer reaches 9.2μF/mm³, showing a rule that the capacitance density is nearly doubled when the thickness is halved, but it is not completely linear. When the thickness is reduced to less than 1μm, the growth rate of capacitance density slows down, which is related to the integrity of the crystalline phase structure inside the dielectric layer.

2. Voltage withstand performance: The voltage withstand value is the maximum DC voltage that MLCC can withstand for a long time at the rated temperature. The test data show that the rated voltage withstand value of MLCC with 3μm dielectric layer is 25V, that of 2μm specification is reduced to 16V, and that of 1μm specification is only 8V. Meanwhile, the voltage withstand consistency was tested, the standard deviation of voltage withstand value of 3μm specification is 0.5V, that of 2μm is 0.8V, and that of 1μm reaches 1.2V, indicating that the thinner the dielectric layer, the greater the dispersion of voltage withstand performance.

3. Dissipation Factor (DF): Dissipation factor reflects the energy loss of MLCC under high-frequency operation. The test data show that the DF value of 3μm dielectric layer is 0.0012, that of 2μm is 0.0015, and that of 1μm is 0.0018, all of which are within the industry general standard (≤0.002), indicating that the impact of thickness reduction on dissipation factor is controllable and does not exceed the commercial threshold.

4. Reliability test: A 1000-hour high-temperature load test was carried out on the three groups of samples, the temperature is 125℃ and DC voltage of 80% of the rated voltage withstand value is applied. The number of failed MLCC with 3μm dielectric layer is 0/100 samples, that of 2μm is 3/100 samples, and that of 1μm is 11/100 samples. The main failure mode is dielectric layer insulation breakdown, indicating that the long-term reliability of thin dielectric layer needs further optimization.

Process Details of Thickness Optimization

The reduction of dielectric layer thickness relies on the precise control of tape casting process, and the core process parameters are as follows: 1. Tape casting slurry formula: the slurry for thin dielectric layer needs to reduce the particle size of ceramic powder, the powder particle size corresponding to 3μm dielectric layer is 0.8μm, and that corresponding to 1μm dielectric layer is 0.3μm, and adjust the proportion of organic binder to ensure slurry uniformity. The test shows that when the powder particle size deviation exceeds 0.05μm, the standard deviation of dielectric layer thickness uniformity will rise to more than 0.1μm; 2. Tape casting speed: the tape casting speed of 3μm dielectric layer is 1.2m/min, that of 2μm is 0.8m/min, and that of 1μm needs to be reduced to 0.5m/min. Excessively fast speed is likely to cause defects such as pinholes and uneven thickness of dielectric layer; 3. Lamination precision: high-precision laminating machine is adopted, and the lamination alignment error is controlled within ±0.02mm. In the lamination process of 1μm dielectric layer, the alignment error exceeding 0.03mm will lead to the dislocation between internal electrode and dielectric layer, directly reducing the capacitance value by more than 10%; 4. Sintering process: the sintering temperature of thin dielectric layer needs to be reduced by 50-80℃, the sintering temperature of 3μm dielectric layer is 1250℃, and that of 1μm is 1180℃, and the holding time is extended by 2 hours to avoid dielectric layer cracking. The test shows that the temperature deviation of ±10℃ in sintering will lead to a decrease of more than 5% in the density of 1μm dielectric layer.

Current Status of Commercial Application

From the perspective of the industry's commercialization progress, MLCC with 3μm dielectric layer is still the mainstream specification in the current consumer electronics and industrial control fields, which has achieved large-scale commercialization worldwide with a market share of about 65%; MLCC with 2μm dielectric layer has achieved large-scale commercialization in mid-to-high end smartphones and portable electronic devices by virtue of its advantages of balancing capacitance density and reliability, with a market share of about 30%; limited by reliability and process yield problems, MLCC with 1μm dielectric layer has only achieved small-batch mass production in some highly integrated miniaturized equipment with a yield of about 75%, the yield rates of 3μm and 2μm specifications are 92% and 85% respectively, which has not reached the economic threshold for large-scale commercialization. In addition, in high-reliability fields such as automotive electronics, the thickness of dielectric layer is still mainly 3μm and above, and only sample verification has been completed for 1μm and 2μm specifications without entering mass production stage.

Existing Technical Pain Points

1. Voltage withstand consistency problem: the dispersion of voltage withstand value of thin dielectric layer MLCC increases significantly with the reduction of thickness, the standard deviation of voltage withstand value of 1μm specification reaches 1.2V, far exceeding the industry general standard of ≤1.0V, which leads to the need for larger voltage margin reserved by downstream application terminals and weakens the miniaturization advantage; 2. Risk of interlayer cracking in sintering: during the high-temperature sintering process of 1μm dielectric layer, microcracks between layers are prone to occur due to the difference in thermal expansion coefficient between internal electrode and dielectric layer. The test shows that the crack incidence rate of MLCC with 1μm specification is about 8% after sintering, while that of 3μm specification is only 1%, and cracks will directly lead to the decrease of insulation resistance and the increase of leakage current; 3. Difficulty in cost control: the slurry cost of 1μm dielectric layer MLCC is about 40% higher than that of 3μm specification, and the equipment precision requirements for tape casting and lamination processes are higher, with the equipment depreciation cost increased by 25%. Even if the yield is increased to 85%, the unit cost is still 30% higher than that of 3μm specification, which restricts its large-scale promotion; 4. High test and verification cost: the reliability test cycle of thin dielectric layer MLCC is longer, the time cost of 1000-hour high-temperature load test is 1.5 times that of 3μm specification, and an accelerated aging test link needs to be added, which further increases the R&D and mass production verification costs.